1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a redundant memory device which can replace defective memory cells (referred to as defective cells hereinafter) within an ordinary memory cell array by reserve memory cells (referred to as reserve cells hereinafter) formed on the same memory chip.
2. Description of the Prior Art
High level of integration and large memory capacity of semiconductor memory devices have been advancing steadily, and the memory capacity per memory chip has been increased at a rate of quadruple in about three years. Four megabit dynamic random access memory (referred to as dram hereinafter) is now already being mass produced, and 16 M DRAM is showing up in the market.
Accompanying the advancement in the high level of integration and the large memory capacity, the probability of including defective cells in the memory cell array is being increased. Under these circumstances, it has been general practice, since the time of the introduction of the 64k DRAM, to employ a technique of suppressing the reduction of the yield for memory production by providing on the memory chip a means for replacing defective cells by reserve cells.
A redundant memory device of the above-mentioned type has an ordinary memory cell array which includes a large number of word lines arranged parallel with each other in row direction and a large number of bit lines arranged parallel with each other in column direction and a large number of memory cells arranged respectively at the intersections of these word lines and these bit lines, a row decoder and a column decoder which selects one of the word lines and one of the bit lines, respectively, in response to an input address code, a large number of sense amplifiers/bit drivers that are connected respectively to the bit lines, address buffers/registers and input and output data buffers/registers that are connected respectively to the row and column decoders and the sense amplifiers/bit drivers, and a control circuit which generates required control pulse in response to a write control signal, a chip selection signal, and a timing signal, that are included as components in an ordinary memory device. In addition to the above, the device is equipped with reserve rows or reserve columns (referred to as reserve rows/columns hereinafter) which consist of a large number of reserve memory cells (referred to as reserve cells hereinafter) that are arranged in the row or column direction adjacent to the ordinary memory cell array, in order to make it possible to replace functionally insufficient defective cells among the large number of memory cells in the unit of row or column to which these defective cells belong, and comparison and selection means which stores the address of a defective cell and selects the reserve row/column in response to the agreement between the input address code word and the address of the stored defective cell. The above-mentioned defective cell is automatically detected during the inspection process of the memory chip production by an ordinary test equipment, and its address is automatically stored in the comparison and selection means within the chip.
The comparison and selection means is equipped with a MOS switching transistor train which includes gate electrodes that respectively receive input address code words that are supplied in bit parallel mode, source electrodes that are respectively connected to the grounding potential, and drain electrodes which are connected to a driving pulse source via respective ones of a plurality of fuse elements that constitute a nonrewritable ROM that stores the address of the defective cell. The common connection side of the fuse elements that are connected to the driving pulse source is connected to the reserve rows/columns via an output circuit. When the address of the defective cell stored in the ROM agrees with the input address code word, all of the MOS switching transistors are de-energized and the driving pulse is supplied as is to the reserve rows/columns through the output circuit to activate the reserve rows/columns. When the two do not agree, the driving pulse is brought to the grounding potential through either one of the MOS switching transistors without activating the reserve rows/columns.
As described in the above, the generation of a pulse output for activation of the reserve rows/columns by the comparison and selection means is accompanied by the drop of the driving pulse to the grounding potential, and hence is accompanied by a power consumption. Moreover, since the driving pulse is also supplied in parallel to the surplus reserve rows/columns that are not needed for the replacement of the defective rows/columns, power consumption takes place in each of these surplus reserve rows/columns, which amounts to a power consumption of considerable level when considered for the memory chip as a whole. An increase in the quantity of power consumption brings about a rise of the temperature of the memory chip, making a large scale integration difficult to be accomplished.